Z8F0113HJ005EG Datasheet, PDF (91/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
76
PWM Period (s) = -------^R----^e---^l-^o---^a---^d-----^V----^a---^l-^u---^e----^----^P----^r--^e---^s--^c---^a---^l-^e--------
System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is represented
by the following equation:
PWM Output High Time Ratio (%) = ^R----^e---^l--^o---^a---^d----^V----^a---^l-^u---^e-----^–----^P----^W-----^M------^V----^a---^l-^u---^e--  100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is represented
by the following equation:
PWM Output High Time Ratio (%) = ---P----W-----M-------V----a---l--u---e----  100
Reload Value
PWM Dual Output Mode
In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic
PWM signal and its complement) through two GPIO port pins. The timer input is the sys-
tem clock. The timer first counts up to the 16-bit PWM match value stored in the Timer
PWM High and Low Byte registers. When the timer count value matches the PWM value,
the Timer Output toggles. The timer continues counting until it reaches the reload value
stored in the Timer Reload High and Low Byte registers. Upon reaching the reload value,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the reload value and is
reset to 0001H.
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A pro-
grammable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a low to a high (inactive to active). This
ensures a time gap between the deassertion of one PWM output to the assertion of its com-
plement.
PS024315-1011
PRELIMINARY
Operation