Z8F0113HJ005EG Datasheet, PDF (135/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
120
The window remains open until the count again reaches 8 (that is, 24 baud clock periods
since the previous pulse was detected), giving the endec a sampling window of minus four
baud rate clocks to plus eight baud rate clocks around the expected time of an incoming
pulse. If an incoming pulse is detected inside this window this process is repeated. If the
incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for
the next falling edge. As each falling edge is detected, the endec clock counter is reset,
resynchronizing the endec to the incoming signal, allowing the endec to tolerate jitter and
baud rate errors in the incoming datastream. Resynchronizing the endec does not alter the
operation of the UART, which ultimately receives the data. The UART is only synchro-
nized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART control regis-
ters as defined in the Universal Asynchronous Receiver/Transmitter chapter on page 97.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART
Control 1 Register to 1 to enable the endec before enabling the GPIO port alternate func-
tion for the corresponding pin.
PS024315-1011
P R E L I M I N A R Y Infrared Encoder/Decoder Control Register