Z8F0113HJ005EG Datasheet, PDF (104/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
89
Bit
[6]
TPOL
(cont’d.)
Description (Continued)
COUNTER Mode
If the timer is enabled the Timer Output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
1 = Count occurs on the falling edge of the Timer Input signal.
PWM SINGLE OUTPUT Mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output
is forced High (1) upon PWM count match and forced Low (0) upon reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Out-
put is forced Low (0) upon PWM count match and forced High (1) upon reload.
CAPTURE Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
GATED Mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the
falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the
rising edge of the Timer Input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current count is
captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current count is
captured on subsequent falling edges of the Timer Input signal.
PWM DUAL OUTPUT Mode
0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the
timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count
match and forced Low (0) upon reload. When enabled, the Timer Output Complement is
forced Low (0) upon PWM count match and forced High (1) upon reload. The PWMD field
in TxCTL0 register is a programmable delay to control the number of cycles time delay
before the Timer Output and the Timer Output Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the
timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count
match and forced High (1) upon reload.When enabled, the Timer Output Complement is
forced High (1) upon PWM count match and forced Low (0) upon reload. The PWMD field
in TxCTL0 register is a programmable delay to control the number of cycles time delay
before the Timer Output and the Timer Output Complement is forced to Low (0).
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
PS024315-1011
PRELIMINARY
Timer Control Register Definitions