Z8F0113HJ005EG Datasheet, PDF (40/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
25
V_CC = 3.3 V
V_POR
V_VBO
Program
Execution
Voltage
Brown-Out
V_CC = 3.3 V
Program
Execution
WDT Clock
System Clock
Internal RESET
signal
Note: Not to Scale
POR
counter delay
Figure 6. Voltage Brown-Out Reset Operation
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a POR after recovering from a VBO condition.
Watchdog Timer Reset
If the device is in NORMAL or STOP Mode, the Watchdog Timer can initiate a System
Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the
unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it
configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control Register is set to signify that the reset was initi-
ated by the Watchdog Timer.
External Reset Input
The RESET pin has a Schmitt-Triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
PS024315-1011
PRELIMINARY
Reset Sources