Z8F0113HJ005EG Datasheet, PDF (38/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
23
Reset Sources
Table 10 lists the possible sources of a System Reset.
Table 10. Reset Sources and Resulting Reset Type
Operating Mode Reset Source
NORMAL or HALT Power-On Reset/Voltage Brown-
modes
Out.
Watchdog Timer time-out when
configured for Reset.
RESET pin assertion.
STOP Mode
OCD initiated Reset (OCDCTL[0]
set to 1).
Power-On Reset/Voltage Brown-
Out.
RESET pin assertion.
DBG pin driven Low.
Special Conditions
Reset delay begins after supply voltage exceeds
POR level.
None.
All reset pulses less than three system clocks in
width are ignored.
System Reset, except the OCD is unaffected by
the reset.
Reset delay begins after supply voltage exceeds
POR level.
All reset pulses less than the specified analog
delay are ignored. See the Electrical Characteris-
tics chapter on page 196.
None.
Power-On Reset
Each device in the Z8 Encore! XP F0823 Series contains an internal POR circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (V_POR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer.
After the Z8 Encore! XP F0823 Series device exits the POR state, the eZ8 CPU fetches the
Reset vector. Following the POR, the POR status bit in Watchdog Timer Control
(WDTCTL) Register is set to 1.
Figure 5 displays POR operation. For the POR threshold voltage (V_POR), see the Electri-
cal Characteristics chapter on page 196.
PS024315-1011
PRELIMINARY
Reset Sources