Z8F0113HJ005EG Datasheet, PDF (78/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
63
Bit
Description (Continued)
[5]
Timer 0 Interrupt Request Enable Low Bit
T0ENL
[4]
UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3]
UART 0 Transmit Interrupt Request Enable Low Bit
U0TENL
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
IRQ1 Enable High and Low Bit Registers
Table 42 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters (Table 43 and Table 44) form a priority-encoded enabling for interrupts in the Inter-
rupt Request 1 Register. Priority is generated by setting bits in each register.
Table 42. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x]
0
0
0
1
1
0
1
1
Note: x indicates register bits 0–7.
Priority
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
Nominal
High
PS024315-1011
PRELIMINARY
Interrupt Control Register Definitions