Z8F0113HJ005EG Datasheet, PDF (81/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
66
Table 47. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
7
Field
RESET
0
R/W
R/W
Address
6
5
Reserved
0
0
R/W
R/W
4
3
C3ENL
0
0
R/W
R/W
FC8H
2
C2ENL
0
R/W
Bit
[7:4]
[3]
C3ENL
[2]
C2ENL
[1]
C1ENL
[0]
C0ENL
Description
Reserved
These bits are reserved and must be programmed to 0000.
Port C3 Interrupt Request Enable Low Bit
Port C2 Interrupt Request Enable Low Bit
Port C1 Interrupt Request Enable Low Bit
Port C0 Interrupt Request Enable High Low
1
C1ENL
0
R/W
0
C0ENL
0
R/W
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) Register (Table 48) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input
pin.
Table 48. Interrupt Edge Select Register (IRQES)
Bit
Field
RESET
R/W
Address
7
IES7
0
R/W
6
IES6
0
R/W
5
IES5
0
R/W
4
IES4
3
IES3
0
0
R/W
R/W
FCDH
2
IES2
0
R/W
1
IES1
0
R/W
0
IES0
0
R/W
Bit
Description
[7]
IESx
Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input PDx.
Note: x indicates the specific GPIO port pin number (7–0).
PS024315-1011
PRELIMINARY
Interrupt Control Register Definitions