Z8F0113HJ005EG Datasheet, PDF (102/245 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F0823 Series
Product Specification
87
two bits to configure timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
Table 57. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
Field
TMODEHI
RESET
0
R/W
R/W
Address
6
5
TICONFIG
0
0
R/W
R/W
4
3
Reserved
0
0
R/W
R/W
F06H, F0EH
2
PWMD
0
R/W
1
0
INPCAP
0
0
R/W
R/W
Bit
[7]
TMODEHI
[6:5]
TICONFIG
[4]
[3:1]
PWMD
[0]
INPCAP
Description
Timer Mode High Bit
This bit along with the TMODE field in TxCTL1 Register determines the operating mode of
the timer. This is the most-significant bit of the Timer mode selection value.
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined reload, compare and input events.
10 = Timer Interrupt only on defined input capture/deassertion events.
11 = Timer Interrupt only on defined reload/compare events.
Reserved
This bit is reserved and must be programmed to 0.
PWMD—PWM Delay value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input capture event.
0 = Previous timer interrupt is not a result of Timer Input capture event.
1 = Previous timer interrupt is a result of Timer Input capture event.
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
PS024315-1011
PRELIMINARY
Timer Control Register Definitions