W631GG6KB-15 Datasheet, PDF (98/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.3 DC & AC Operating Conditions
9.3.1 Recommended DC Operating Conditions
SYM.
PARAMETER
MIN.
TYP. MAX.
VDD Supply Voltage
1.425
1.5
1.575
VDDQ Supply Voltage for Output
1.425
1.5
1.575
RZQ
External Calibration Resistor connected
from ZQ ball to ground
237.6
240.0
242.4
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The external calibration resistor RZQ can be time-shared among DRAMs in special applications.
9.4 Input and Output Leakage Currents
UNIT
V
V
Ω
NOTES
1, 2
1, 2
3
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTES
Input Leakage Current
IIL
(0V ≤ VIN ≤ VDD)
-2
2
µA
1
Output Leakage Current
IOL
-5
5
µA
2
(Output disabled, 0V ≤ VOUT ≤ VDDQ)
Notes:
1. All other balls not under test = 0 V.
2. All DQ, DQS and DQS# are in high-impedance mode.
9.5 Interface Test Conditions
Figure 88 represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of
the actual load presented by a production tester. System designers should use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers
correlate to their production test conditions, generally one or more coaxial transmission lines
terminated at the tester electronics.
VDDQ
CK, CK#
DUT
DQ
DQS
DQS#
VTT = VDDQ/2
25Ω
Timing reference point
Figure 88 – Reference Load for AC Timings and Output Slew Rates
The Timing Reference Points are the idealized input and output nodes / terminals on the outside of the
packaged SDRAM device as they would appear in a schematic or an IBIS model.
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g.
DQSL, DQSU) and the complement (e.g. DQSL#, DQSU#) signal.
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Publication Release Date: Feb. 27, 2013
Revision A04