W631GG6KB-15 Datasheet, PDF (146/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
17.When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the actual
SDRAM input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has tERR(mper),act,min = - 138 pS and
tERR(mper),act,max = + 155 pS, then
tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 255 pS - 155 pS = - 410 pS and
tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 255 pS + 138 pS = + 393 pS.
Similarly, tLZ(DQ) for DDR3-1333 derates to tLZ(DQ),min(derated) = - 500 pS - 155 pS = - 655 pS and
tLZ(DQ),max(derated) = 250 pS + 138 pS = + 388 pS. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and
tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
18.When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has tCK(avg),act = 1500 pS,
tJIT(per),act,min = - 58 pS and tJIT(per),act,max = + 74 pS, then
tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 1500
pS - 58 pS = + 1292 pS.
Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x
1500 pS - 58 pS = + 512 pS. (Caution on the min/max usage!).
19.WR in clock cycles as programmed in mode register MR0.
20.tWR(min) is defined in nS, for calculation of tWRPDEN it is necessary to round up tWR(min)/tCK(avg) to the
next integer value.
21.The maximum read preamble is bound by tLZ(DQS)min on the left side and tDQSCK(max) on the right side.
See Figure 24 - “READ Timing; Clock to Data Strobe relationship” on page 44.
22.The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max
on the right side. See Figure 24 - “READ Timing; Clock to Data Strobe relationship” on page 44.
23.Value is only valid for RON34.
24.Single ended signal parameter.
25.tREFI depends on TOPER.
26.Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
27.CKE is allowed to be registered low while operations such as row activation, precharge, auto-precharge
or refresh are in progress, but power down IDD spec will not be applied until finishing those operations.
28.Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is
satisfied, there are cases where additional time such as tXPDLL(min) is also required. See section 7.17.3
“Power-Down clarifications - Case 2” on page 74.
29.Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
30.ODTH4 is measured from ODT first registered high (without a Write command) to ODT first registered
low, or from ODT registered high together with a Write command with burst length 4 to ODT registered
low.
31.ODTH8 is measured from ODT registered high together with a Write command with burst length 8 to
ODT registered low.
32.This parameter applies upon entry and during precharge power down mode with DLL frozen.
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Publication Release Date: Feb. 27, 2013
Revision A04