W631GG6KB-15 Datasheet, PDF(155/158 Page) Winbond – Double Data Rate architecture: two data transfers per clock cycle

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

W631GG6KB-15 Datasheet, PDF (155/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

◁

W631GG6KB

9.16.5 Data Setup, Hold and Slew Rate Derating

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the

data sheet tDS(base) and tDH(base) value (see Table 54) to the ÎtDS and ÎtDH (see Table 55 and Table

56) derating value respectively. Example: tDS (total setup time) = tDS(base) + ÎtDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing

of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is

defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max

(see Figure 107). If the actual signal is always earlier than the nominal slew rate line between shaded

âVREF(DC) to AC regionâ, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded âVREF(DC) to AC regionâ, the slew rate of a tangent

line to the actual signal from the AC level to VREF(DC) level is used for derating value (see Figure 109).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is

defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)

(see Figure 108). If the actual signal is always later than the nominal slew rate line between shaded

âDC level to VREF(DC) regionâ, use nominal slew rate for derating value. If the actual signal is earlier

than the nominal slew rate line anywhere between shaded âDC to VREF(DC) regionâ, the slew rate of a

tangent line to the actual signal from the DC level to VREF(DC) level is used for derating value (see

Figure 110).

For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see

Table 57).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not

have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to

complete the transition and reach VIH/IL(AC).

For slew rates in between the values listed in the tables the derating values may obtained by linear

interpolation.

These values are typically not subject to production test. They are verified by design and

characterization.

Table 54 â Data Setup and Hold Base-Values

Symbol

Reference

DDR3-1333 DDR3-1600

tDS(base) AC150

VIH/L(AC)

SR=1V/nS

tDS(base) AC135

VIH/L(AC)

SR=2V/nS

tDH(base) DC100

VIH/L(DC)

SR=1V/nS

tDH(base) DC100

VIH/L(DC)

SR=2V/nS

Notes:

1. (AC/DC referenced for 2V/nS DQ-slew rate and 4 V/nS DQS slew rate).

2. (AC/DC referenced for 1V/nS DQ-slew rate and 2 V/nS DQS slew rate).

DDR3-1866

Unit

Notes

- 155 -

Publication Release Date: Feb. 27, 2013

Revision A04

▷