W631GG6KB-15 Datasheet, PDF (27/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.8 Input clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be ―stable‖ during
almost all states of normal operation. This means that, once the clock frequency has been set and is
to be in the ―stable state‖, the clock period is not allowed to deviate except for what is allowed for by
the clock jitter and SSC (spread spectrum clocking) specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate
under two conditions: (1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these
two modes, it is illegal to change the clock frequency.
7.8.1 Frequency change during Self-Refresh
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode
and tCKSRE has been satisfied, the state of the clock becomes a don't care. Once a don't care,
changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX.
When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency,
the Self-Refresh entry and exit specifications must still be met as outlined in see section 7.16 “Self-
Refresh Operation” on page 66.
The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change below the
minimum operating frequency would require the use of DLL_on mode -> DLL_off mode transition
sequence; refer to section 7.7 “DLL on/off switching procedure” on page 25.
7.8.2 Frequency change during Precharge Power-down
The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit
mode or slow exit mode). If the Rtt_Nom feature was enabled in the mode register prior to entering
Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is
in an off state. If the Rtt_Nom feature was disabled in the mode register prior to entering Precharge
power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or
HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency
may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum
and maximum operating frequency specified for the particular speed grade. During the input clock
frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency
is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down
may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET
via MRS. Depending on the new clock frequency, additional MRS commands may need to be issued
to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock
period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is
ready to operate with new clock frequency. This process is depicted in Figure 12 on page 28.
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Publication Release Date: Feb. 27, 2013
Revision A04