W631GG6KB-15 Datasheet, PDF (154/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
CK
CK#
DQS#
DQS
tDS
tDH
VDDQ
tIS
tIH
tDS
tDH
VIH(AC)min
VIH(DC)min
DC to VREF
region
VREF(DC)
VIL(DC)max
DC to VREF
region
VIL(AC)max
tangent
line
nominal
line
tangent
line
nominal
line
VSS
ΔTR
Hold Slew Rate ^{tangent line [VREF(DC) - VIL(DC)max]}
Rising Signal ⁼
ΔTR
ΔTF
Hold Slew Rate ^{tangent line [VIH(DC)min - VREF(DC)]}
Falling Signal ⁼
ΔTF
Figure 110 – Illustration of tangent line for for hold time tDH (for DQ with respect to strobe) and
tIH (for ADD/CMD with respect to clock)
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Publication Release Date: Feb. 27, 2013
Revision A04