W631GG6KB-15 Datasheet, PDF (137/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.16 AC Characteristics
9.16.1 AC Timing and Operating Condition for -11 speed grade
SYMBOL
Common Notes
SPEED GRADE
PARAMETER
DDR3-1866 (-11)
MIN.
MAX.
Clock Input Timing
tCK(DLL-off) Minimum clock cycle time (DLL-off mode)
8

tCK(avg) Average Clock Period
See ―Speed Bin‖ on page 135
tCH(avg) Average CK/CK# high pulse width
0.47
0.53
tCL(avg) Average CK/CK# low pulse width
0.47
0.53
tCK(abs) Absolute Clock Period
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
tCH(abs) Absolute CK/CK# high pulse width
0.43

tCL(abs) Absolute CK/CK# low pulse width
0.43

tJIT(per) Clock Period Jitter
-60
60
tJIT(per,lck) Clock Period Jitter during DLL locking period
-50
50
tJIT(cc) Cycle to Cycle Period Jitter
120
tJIT(cc,lck)
Cycle to Cycle Period Jitter during DLL locking
period
100
tJIT(duty) Clock Duty Cycle Jitter
Already included in tCH(abs) and
tCL(abs)
tERR(2per) Cumulative error across 2 cycles
-88
88
tERR(3per) Cumulative error across 3 cycles
-105
105
tERR(4per) Cumulative error across 4 cycles
-117
117
tERR(5per) Cumulative error across 5 cycles
-126
126
tERR(6per) Cumulative error across 6 cycles
-133
133
tERR(7per) Cumulative error across 7 cycles
-139
139
tERR(8per) Cumulative error across 8 cycles
-145
145
tERR(9per) Cumulative error across 9 cycles
-150
150
tERR(10per) Cumulative error across 10 cycles
-154
154
tERR(11per) Cumulative error across 11 cycles
-158
158
tERR(12per) Cumulative error across 12 cycles
-161
161
tERR(nper)
Cumulative error across n = 13, 14...49, 50
cycles
Min.: tJIT(per)min * (1 + 0.68 * ln(n))
Max.: tJIT(per)max * (1 + 0.68 * ln(n))
UNITS NOTES
1, 2, 3, 4
nS
45
pS
tCK(avg)
tCK(avg)
pS
37
tCK(avg)
38
tCK(avg)
39
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
7
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Publication Release Date: Feb. 27, 2013
Revision A04