W631GG6KB-15 Datasheet, PDF (111/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.8.1 Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 30
and Table 31.
ΔT = T - T(@calibration); ΔV= VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Table 30 – Output Driver Sensitivity Definition
RONPU@ VOHDC
RON@ VOMDC
RONPD@ VOLDC
MIN.
0.6 - dRONdTH*|ΔT| - dRONdVH*|ΔV|
0.9 - dRONdTM*|ΔT| - dRONdVM*|ΔV|
0.6 - dRONdTL*|ΔT| - dRONdVL*|ΔV|
MAX.
1.1 + dRONdTH*|ΔT| + dRONdVH*|ΔV|
1.1 + dRONdTM*|ΔT| + dRONdVM*|ΔV|
1.1 + dRONdTL*|ΔT| + dRONdVL*|ΔV|
UNIT
RZQ/7
RZQ/7
RZQ/7
Table 31 – Output Driver Voltage and Temperature Sensitivity
Speed Bin
DDR3-1333
MIN.
MAX.
DDR3-1600 & DDR3-1866
MIN.
MAX.
UNIT
dRONdTM
0
1.5
0
1.5
%/°C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/°C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/°C
dRONdVH
0
0.15
0
0.13
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
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Publication Release Date: Feb. 27, 2013
Revision A04