W631GG6KB-15 Datasheet, PDF (96/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
8.3 Simplified State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and
the commands to control them. In particular, situations involving more than one bank, the enabling or
disabling of on-die termination, and some other events are not captured in full detail.
Power
Applied
Power
on
Reset
Procedure
From any state
RESET
Initialization
MRS, MPR,
Write
Leveling
ZQCL
MRS
ZQCL, ZQCS
ZQ
Calibration
Idle
SRE
SRX
REF
CKE_ L
Self
Refresh
Refreshing
ACT
PDE
PDX
Active
Power
Down
CKE_L
Activating
PDX
PDE
Precharge
Power
Down
CKE_L
Write
Write
Bank
Active
Read
Write A Read A
Writing
Read
Write
Reading
Read
Write A
Writing
Write A
PRE, PREA
PRE, PREA PRE, PREA
Read A
Reading
Precharging
Automatic sequence
Command sequence
Figure 87 – Simplified State Diagram
Table 16 – State Diagram Command Definitions
Abbreviation
ACT
PRE
PREA
MRS
REF
ZQCL
Function
Abbreviation
Function
Abbreviation
Active
Read
RD, RDS4, RDS8
PDE
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Precharge All
Write
WR, WRS4, WRS8
SRE
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Refresh
RESET
Start RESET Procedure
MPR
ZQ Calibration Long
ZQCS
ZQ Calibration Short
-
NOTE: See “Command Truth Table” on page 93 for more details
Function
Enter Power-down
Exit Power-down
Self-Refresh entry
Self-Refresh exit
Multi-Purpose Register
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Publication Release Date: Feb. 27, 2013
Revision A04