W631GG6KB-15 Datasheet, PDF (135/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.15.3 DDR3-1866 Speed Bin and Operating Conditions
Speed Bin
DDR3-1866
CL-nRCD-nRP
13-13-13
Part Number Extension
-11
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX

933
Internal read command to first data
tAA
13.91
20
ACT to internal read or write delay time
tRCD
13.91

PRE command period
tRP
13.91

ACT to ACT or REF command period
tRC
47.91

ACT to PRE command period
tRAS
34
9 * tREFI
CL = 6
CWL = 5
CWL = 6, 7, 8, 9
tCK(AVG)
tCK(AVG)
2.5
3.3
Reserved
CL = 8
CWL = 5
CWL = 6
CWL = 7, 8, 9
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
1.875
<2.5
Reserved
CL =10
CWL = 5, 6
CWL = 7
tCK(AVG)
tCK(AVG)
Reserved
1.5
<1.875
CL =13
CWL = 8, 9
CWL = 5, 6, 7, 8
CWL = 9
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
Reserved
1.07
<1.25
Supported CL Settings
Sup_CL
6, 8, 10, 13
Supported CWL Settings
Sup_CWL
5, 6, 7, 9
UNIT NOTES
MHz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nCK
nCK
1,2,3,4,8
5
5
1,2,3,4,8
5
5
1,2,3,4,8
5
5
1,2,3,4,8
- 135 -
Publication Release Date: Feb. 27, 2013
Revision A04