W631GG6KB-15 Datasheet, PDF (7/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
4. KEY PARAMETERS
Speed Bin
CL-nRCD-nRP
Part Number Extension
Parameter
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
Internal read command to first data
Sym.
fCKMAX
tAA
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
tRC
ACT to PRE command period
tRAS
CL = 6
CWL = 5 tCK(AVG)
CL = 7
CWL = 6 tCK(AVG)
CL = 8
CWL = 6 tCK(AVG)
CL = 9
CWL = 7 tCK(AVG)
CL = 10
CWL = 7 tCK(AVG)
CL = 11
CWL = 8 tCK(AVG)
CL = 13
CWL = 9 tCK(AVG)
Supported CL Settings
Sup_CL
Supported CWL Settings
Sup_CWL
-40°C ≤ TCASE ≤ 85°C
Average periodic
refresh Interval
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
tREFI
95°C < TCASE ≤ 105°C
Operating One Bank Active-Precharge Current IDD0
Operating One Bank Active-Read-Precharge
Current
IDD1
Operating Burst Read Current
IDD4R
Operating Burst Write Current
IDD4W
Burst Refresh Current
IDD5B
Self-Refresh Current, T_OPER = 0 ~ 85°C
IDD6
Operating Bank Interleave Current
IDD7
DDR3-1866
13-13-13
-11
Min. Max.
DDR3-1600
DDR3-1333
11-11-11
9-9-9
Unit
-12/12I/12A/12K -15/15I/15A/15K
Min. Max. Min. Max.

933

800

667 MHz
13.91
13.91
13.91
47.91
13.75
13.5
20
(13.125)⁷
20
(13.125)⁷
20
13.75
13.5

(13.125)⁷

(13.125)⁷

13.75
13.5

(13.125)⁷

(13.125)⁷

48.75
49.5

(48.125)⁷

(49.125)⁷

34
9 * tREFI
35
9 * tREFI
36
9 * tREFI
2.5
3.3
2.5
3.3
2.5
3.3
Reserved
1.875
<2.5
1.875
<2.5
1.875
<2.5
1.875
<2.5
1.875
<2.5
Reserved
1.5
<1.875
1.5
<1.875
1.5
<1.875
1.5
<1.875
1.5
<1.875
Reserved
1.25
<1.5
Reserved
1.07
<1.25
Reserved
Reserved
6, 8, 10, 13
6, (7), 8, (9), 10, 11
6, (7), 8, 9, 10
5, 6, 7, 9

*²
5, 6, 7, 8

7.8 *^{2, 3}
5, 6, 7

7.8 *^{2, 3}

7.8 *¹

7.8 *¹

7.8 *¹

3.9 *⁴

3.9 *⁴

3.9 *⁴

*⁶

3.9 *^{5, 6}

3.9 *^{5, 6}

130

115

105
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nCK
nCK
μS
μS
μS
μS
mA

165

145

130
mA

330

280

240
mA

260

220

190
mA

185

170

160
mA

14

14

14
mA

430

400

380
mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤ TCASE < 0°C is not available.
3. 12I, 12A, 12K, 15I, 15A and 15K speed grades support -40°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0_b and MR2 A7 = 1_b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1_b, MR2 A7 is don't care).
5. For 12K and 15K automotive parts, TCASE is able to extend to 105°C with doubling Auto Refresh commands in frequency to a
32 mS period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0_b and MR2 A7 = 1_b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1_b, MR2 A7 is
don't care).
6. For -11, -12, 12I, 12A, -15, 15I and 15A speed grade parts, 95°C < TCASE ≤ 105°C is not available.
7. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings
must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)
should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11)
devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for
tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21,
23) also should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333
(9-9-9) and 48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
Publication Release Date: Feb. 27, 2013
Revision A04
-7-