W631GG6KB-15 Datasheet, PDF (14/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.3 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode
Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed
via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not
defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after
power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by
re-executing the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after
power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the
mode register and is the minimum time required between two MRS commands shown in Figure 3.
T0
CK#
CK
Command
VALID
T1
VALID
T2
VALID
Ta0
MRS
Address
VALID
VALID
VALID
VALID
CKE
Settings
Old settings
Rtt_Nom ENABLED prior and/or after MRS command
ODT
VALID
VALID
ODTLoff+1
Rtt_Nom DISABLED prior and/or after MRS command
ODT
VALID
VALID
VALID
VALID
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
NOP/DES
NOP/DES
VALID
VALID
MRS
VALID
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
tMRD
Updating Settings
tMOD
New Settings
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
VALID
DON'T CARE
Figure 3 – tMRD Timing
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Publication Release Date: Feb. 27, 2013
Revision A04