W631GG6KB-15 Datasheet, PDF (95/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
8.2 CKE Truth Table
Notes 1-7 apply to the entire CKE Truth Table.
For Power-down entry and exit parameters See 7.17 “Power-Down Modes” on page 68.
CKE low is allowed only if tMRD and tMOD are satisfied.
Table 15 – CKE Truth Table
CURRENT
STATE²
Power Down
CKE
Previous Cycle ¹ Current Cycle ¹
(N-1)
(N)
L
L
L
H
COMMAND (N) ³
RAS#, CAS#, WE#, CS#
X
DESELECT or NOP
ACTION (N) ³
Maintain Power Down
Power Down Exit
NOTES
14,15
11,14
L
Self Refresh
L
L
X
Maintain Self Refresh
15,16
H
DESELECT or NOP
Self Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power Down Entry
11
H
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry 11,13,14,18
L
REFRESH
Self Refresh
9,13,18
Any other state Refer to section 8.1 “Command Truth Table” on Page 93 for more detail with all command signals
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained until 1nCK prior to
tCKEmin being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period.
Read or ODT commands may be issued only after tXSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered during Read or Write operations. For a detailed list of restrictions See section 7.16 “Self-
Refresh Operation” on page 66 and See section 7.17 “Power-Down Modes” on page 68.
14. The Power Down does not perform any refresh operations.
15. ―X‖ means ―don't care‖ (including floating around VREF) in Self Refresh and Power Down. It also applies to Address pins.
16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ supply may be turned OFF
and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VREFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered,
otherwise Active Power Down is entered.
18. ‗Idle state‘ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self Refresh
exit and Power Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
- 95 -
Publication Release Date: Feb. 27, 2013
Revision A04