W631GG6KB-15 Datasheet, PDF (151/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
CK
CK#
DQS#
DQS
tDS
tDH
VDDQ
VIH(AC)min
VIH(DC)min
VREF to AC
region
VREF(DC)
VIL(DC)max
VIL(AC)max
nominal
slew rate
tIS
tIH
tDS
tDH
tVAC
nominal
slew rate
VREF to AC
region
VSS
tVAC
ΔTF
Setup Slew Rate VREF(DC) – VIL(AC)max
Falling Signal ⁼
ΔTF
ΔTR
Setup Slew Rate ^{VIH(AC)min - VREF(DC)}
Rising Signal ⁼
ΔTR
Figure 107 – Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to
strobe) and tIS (for ADD/CMD with respect to clock)
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Publication Release Date: Feb. 27, 2013
Revision A04