W631GG6KB-15 Datasheet, PDF (20/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set
Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally.
7.3.2.2 Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as
shown in Figure 6.
7.3.2.3 ODT RTT Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The
nominal termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be
programmed in MR2 to enable a unique RTT value when ODT is enabled during writes. The Rtt_WR
value can be applied during writes even when Rtt_Nom is disabled.
7.3.2.4 Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command
(either with or without auto-precharge) to be issued immediately after the active command. The
command is held for the time of the Additive Latency (AL) before it is issued inside the device. The
Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write
Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A
summary of the AL register options are shown in Table 2.
Table 2 – Additive Latency (AL) Settings
A4
A3
AL
0
0
0 (AL Disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
Note:
AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.
7.3.2.5 Write leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has the benefit of reducing the number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‗write leveling‘ feature to allow the controller to compensate
for skew. See section 7.9 “Write Leveling” on page 29 for more details.
7.3.2.6 Output Disable
The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 6. When
this feature is enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the
device, thus removing any loading of the output drivers. This feature may be useful when measuring
module power, for example. For normal operation, A12 should be set to ‗0‘.
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Publication Release Date: Feb. 27, 2013
Revision A04