W631GG6KB-15 Datasheet, PDF (142/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
AC Timing and Operating Condition for -12/12I/12A/12K/-15/15I/15A/15K speed grades, continued
SYMBOL
SPEED GRADE
DDR3-1600
(-12/12I/12A/12K)
DDR3-1333
(-15/15I/15A/15K)
UNITS NOTES
PARAMETER
MIN. MAX. MIN. MAX.
Data Timing
tDQSQ DQS, DQS# to DQ skew, per group, per access

100

125
pS
23
tQH
DQ output hold time from DQS, DQS#
0.38

0.38

tCK(avg) 18, 23
tLZ(DQ) DQ low impedance time from CK, CK#
-450
225
-500
250
pS 17, 23, 24
tHZ(DQ) DQ high impedance time from CK, CK#

225

250
pS 17, 23, 24
tDS(AC150)
Data setup time to
DQS, DQS#
Base specification
VREF @ 1 V/nS
10
160
30
180
pS
11, 40
11, 40, 42
tDH(DC100)
Data hold time from
DQS, DQS#
Base specification
VREF @ 1 V/nS
45
145
65
165
pS
11, 40
11, 40, 42
tDIPW DQ and DM input pulse width for each input
360

400

pS
10
Data Strobe Timing
tRPRE DQS,DQS# differential READ Preamble
0.9
Note 21 0.9
Note 21 tCK(avg) 18, 21, 23
tRPST DQS,DQS# differential READ Postamble
0.3
Note 22 0.3
Note 22 tCK(avg) 18, 22, 23
tQSH DQS,DQS# differential output high time
0.4

0.4

tCK(avg) 18, 23
tQSL DQS,DQS# differential output low time
0.4

0.4

tCK(avg) 18, 23
tWPRE DQS,DQS# differential WRITE Preamble
0.9

0.9

tCK(avg)
46
tWPST DQS,DQS# differential WRITE Postamble
0.3

0.3

tCK(avg)
46
tDQSCK
DQS,DQS# rising edge output access time from
rising CK, CK#
-225
225
-255
255
pS
17, 23
tLZ(DQS)
DQS and DQS# low-impedance time from
CK, CK# (Referenced from RL - 1)
-450
225
-500
250
pS 17, 23, 24
tHZ(DQS)
DQS and DQS# high-impedance time from
CK, CK# (Referenced from RL + BL/2)

225

250
pS 17, 23, 24
tDQSL DQS,DQS# differential input low pulse width
0.45
0.55
0.45
0.55 tCK(avg) 12, 14
tDQSH DQS,DQS# differential input high pulse width
0.45
0.55
0.45
0.55 tCK(avg) 13, 14
tDQSS DQS,DQS# rising edge to CK,CK# rising edge
-0.27
0.27 -0.25
0.25 tCK(avg) 16
tDSS
DQS,DQS# falling edge setup time to CK,CK#
rising edge
0.18

0.2

tCK(avg) 15, 16
tDSH
DQS,DQS# falling edge hold time from CK,CK#
rising edge
0.18

0.2

tCK(avg) 15, 16
Command and Address Timing
tAA
Internal read command to first data
nS
8
tRCD
tRP
tRC
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
nS
8
See ―Speed Bin‖ on See ―Speed Bin‖ on
page 134
page 133
nS
8
nS
8
tRAS ACT to PRE command period
nS
8
tDLLK DLL locking time
512

512

nCK
tRTP
Internal READ Command to PRECHARGE
Command delay
max(4nCK,
7.5nS)

max(4nCK,
7.5nS)

8
tWTR
Delay from start of internal write transaction to max(4nCK,
internal read command
7.5nS)

max(4nCK,
7.5nS)

8, 26
- 142 -
Publication Release Date: Feb. 27, 2013
Revision A04