W631GG6KB-15 Datasheet, PDF (125/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Table 40 – IDD0 Measurement-Loop Pattern¹
Data²
0
ACT 0 0 1 1 0 0 0 0 0 0 0
-
1, 2
D, D 1 0 0 0 0 0 0 0 0 0 0
-
3, 4
D#, D# 1 1 1 1 0 0 0 0 0 0 0
-
...
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE 0 0 1 0 0 0 0 0 0 0 0
-
...
Repeat pattern 1...4 until nRC - 1, truncate if necessary
0
1*nRC+0
ACT 0 0 1 1 0 0 0 0 0 F 0
-
1*nRC+1, 2
D, D 1 0 0 0 0 0 0 0 0 F 0
-
1*nRC+3, 4 D#, D# 1 1 1 1 0 0 0 0 0 F 0
-
...
Repeat pattern nRC + 1,...,4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 0 0 0 F 0
-
...
Repeat pattern nRC + 1,...,4 until 2*nRC - 1, truncate if necessary
1
2*nRC
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
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Publication Release Date: Feb. 27, 2013
Revision A04