W631GG6KB-15 Datasheet, PDF (63/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
CK#
CK
Command^*3
T0
T1
WRITE
NOP
T2
NOP
tCCD
T3
T4
T5
NOP
WRITE
NOP
T6
NOP
T7
NOP
T8
NOP
T9
NOP
T10
T11
T12
NOP
NOP
4 clocks
NOP
T13
NOP
Address^*4
Bank
Col n
DQS, DQS#
Bank
Col b
tWPRE
tWPST
DQ^*2
WL = 5
Din
Din
Din
Din
Din
Din
Din
Din
Din
Din
Din
Din
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
b
b+1
b+2
b+3
WL = 5
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T4.
TRANSITIONING DATA
T14
NOP
tWR
tWTR
DON'T CARE
Figure 53 – WRITE (BL8) to WRITE (BC4) OTF
CK#
CK
Command^*3
T0
T1
WRITE
NOP
T2
NOP
tCCD
T3
T4
T5
NOP
WRITE
NOP
T6
NOP
T7
NOP
Address^*4
Bank
Col n
DQS, DQS#
Bank
Col b
tWPRE
tWPST
DQ^*2
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
WL = 5
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T4.
T8
T9
T10
T11
T12
T13
T14
NOP
NOP
tWPRE
NOP
NOP
4 clocks
NOP
NOP
NOP
tWR
tWTR
tWPST
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
B+4
b+5
b+6
b+7
TRANSITIONING DATA
DON'T CARE
Figure 54 – WRITE (BC4) to WRITE (BL8) OTF
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Publication Release Date: Feb. 27, 2013
Revision A04