W631GG6KB-15 Datasheet, PDF(148/158 Page) Winbond – Double Data Rate architecture: two data transfers per clock cycle

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W631GG6KB-15 Datasheet, PDF (148/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

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W631GG6KB

9.16.4 Address / Command Setup, Hold and Derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the

datasheet tIS(base) and tIH(base) value (see Table 48) to the ÎtIS and ÎtIH derating value (see Table 49)

respectively. Example: tIS (total setup time) = tIS(base) + ÎtIS

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is

defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If

the actual signal is always earlier than the nominal slew rate line between shaded âVREF(DC) to AC

regionâ, use nominal slew rate for derating value (see Figure 107). If the actual signal is later than the

nominal slew rate line anywhere between shaded âVREF(DC) to AC regionâ, the slew rate of a tangent

line to the actual signal from the AC level to VREF(DC) level is used for derating value (see Figure 109).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of

VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined

as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual

signal is always later than the nominal slew rate line between shaded âDC to VREF(DC) regionâ, use

nominal slew rate for derating value (see Figure 108). If the actual signal is earlier than the nominal

slew rate line anywhere between shaded âDC to VREF(DC) regionâ, the slew rate of a tangent line to the

actual signal from the DC level to VREF(DC) level is used for derating value (see Figure 110).

For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see

Table 53).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not

have reached VIH/IL(AC) at the time of the rising clock transition, a valid input signal is still required to

complete the transition and reach VIH/IL(AC).

For slew rates in between the values listed in Table 49, the derating values may obtained by linear

interpolation.

These values are typically not subject to production test. They are verified by design and

characterization.

Table 48 â ADD/CMD Setup and Hold Base-Values for 1V/nS

Symbol

Reference

DDR3-1333

DDR3-1600

DDR3-1866

Unit

tIS(base) AC175

VIH/L(AC)

tIS(base) AC150

VIH/L(AC)

190

170

tIS(base) AC135

VIH/L(AC)

tIS(base) AC125

VIH/L(AC)

150

tIH(base) DC100

VIH/L(DC)

140

120

100

Notes:

1. (AC/DC referenced for 1V/nS Address/Command slew rate and 2 V/nS differential CK-CK# slew rate)

2. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 100pS for

DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another 25 pS to account for

the earlier reference point [(175 mV - 150 mV) / 1 V/nS].

3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75pS for

DDR3-1866 of derating to accommodate for the lower alternate threshold of 125 mV and another 10 pS to account for the

earlier reference point [(135 mV - 125 mV) / 1 V/nS].

- 148 -

Publication Release Date: Feb. 27, 2013

Revision A04

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