W631GG6KB-15 Datasheet, PDF (132/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.14 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the
min/max values may result in malfunction of the DDR3 SDRAM device.
Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where
each clock period is calculated from rising edge to rising edge.
^N

 ^{tCK(avg) =}  ^tCK j  ^{/ N}
 ^{j 1}

where N = 200
Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
consecutive rising edge. tCK(abs) is not subject to production test.
Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
^{ N}

tCH(avg) = _ tCH _{j } / (N × tCK(avg))
 ^{j 1}

where N = 200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low
pulses.
^N

 ^{tCL(avg) =}  ^tCL j  ^{/ (N × tCK(avg))}
 ^{j 1}

where N = 200
Definition for tJIT(per) and tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
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Publication Release Date: Feb. 27, 2013
Revision A04