W631GG6KB-15 Datasheet, PDF (100/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.6.2 DC and AC Input Levels for Single-Ended Data Signals
Table 18 – Single-Ended DC and AC Input Levels for DQ and DM
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600
MIN.
MAX.
DDR3-1866
MIN.
MAX.
UNIT NOTES
DC input logic high VIH.DQ(DC100) VREF + 0.100
VDD
VREF + 0.100
VDD
V
1, 5
DC input logic low VIL.DQ(DC100)
VSS
VREF - 0.100
VSS
VREF - 0.100
V
1, 6
AC input logic high VIH.DQ(AC150) VREF + 0.150
Note 2
-
-
V
1, 2, 7
AC input logic low VIL.DQ(AC150)
Note 2
VREF - 0.150
-
-
V
1, 2, 8
AC input logic high VIH.DQ(AC135) VREF + 0.135
Note 2
VREF + 0.135
Note 2
V
1, 2, 7
AC input logic low VIL.DQ(AC135)
Note 2
VREF - 0.135
Note 2
VREF - 0.135
V
1, 2, 8
Reference Voltage
for DQ, DM inputs
VREFDQ(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Notes:
1. VREF = VREFDQ(DC).
2. See section 9.12 “Overshoot and Undershoot Specifications” on page 120.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ(DC) by more than ± 1% VDD (for reference:
approx. ± 15 mV).
4. For reference: approx. VDD/2 ± 15 mV.
5. VIH(DC) is used as a simplified symbol for VIH.DQ(DC100).
6. VIL(DC) is used as a simplified symbol for VIL.DQ(DC100).
7. VIH(AC) is used as a simplified symbol for VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC150) value is used when VREF +
0.150V is referenced, and VIH.DQ(AC135) value is used when VREF + 0.135V is referenced.
8. VIL(AC) is used as a simplified symbol for VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC150) value is used when VREF -
0.150V is referenced, and VIL.DQ(AC135) value is used when VREF - 0.135V is referenced.
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Publication Release Date: Feb. 27, 2013
Revision A04