W631GG6KB-15 Datasheet, PDF (34/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.10.1 MPR Functional Description
 One bit wide logical interface via all DQ pins during READ operation.
 Register Read:
— DQL[0] and DQU[0] drive information from MPR.
— DQL[7:1] and DQU[7:1] either drive the same information as DQL[0].
 Addressing during for Multi Purpose Register reads for all MPR agents:
— BA[2:0]: Don't care
— A[1:0]: A[1:0] must be equal to ‗00‘b. Data read burst order in nibble is fixed
— A[2]: A[2] selects the burst order
For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *)
For Burst Chop 4 cases, the burst order is switched on nibble base
A[2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
— A[9:3]: Don't care
— A10/AP: Don't care
— A11: Don't care
— A12/BC#: Selects burst chop mode on-the-fly, if enabled within MR0
 Regular interface functionality during register reads:
— Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
— Support of read burst chop (MRS and on-the-fly via A12/BC#)
— All other address bits (remaining column address bits including A10, all bank address bits) will
be ignored by the DDR3 SDRAM.
— Regular read latencies and AC timings apply.
— DLL must be locked prior to MPR Reads.
Note: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
- 34 -
Publication Release Date: Feb. 27, 2013
Revision A04