W631GG6KB-15 Datasheet, PDF (123/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Table 39 – Basic IDD and IDDQ Measurement Conditions
SYM.
IDD0
IDD1
IDD2N
IDD2NT
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
DESCRIPTION
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: High
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according
to Table 40; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 40); Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0; Pattern Details: see Table 40
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 38; BL: 8^(1,6); AL: 0; CS#:
High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling according to Table 41; DM: stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,... (see Table 41); Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0; Pattern Details: see Table 41
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 42; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers⁽²⁾; ODT Signal: stable at 0; Pattern Details: see Table 42
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 43; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers⁽²⁾; ODT Signal: toggling according to Table 43; Pattern Details: see Table 43
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0; Pecharge Power Down Mode: Slow Exit⁽³⁾
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0; Pecharge Power Down Mode: Fast Exit⁽³⁾
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 42; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers⁽²⁾; ODT Signal: stable at 0; Pattern Details: see Table 42
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8⁽¹⁾; AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT
Signal: stable at 0
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Publication Release Date: Feb. 27, 2013
Revision A04