W631GG6KB-15 Datasheet, PDF (10/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
E3, F7, F2, F8, H3,
H8, G2, H7
DQL0−DQL7
Input/Output Data Input/Output: Lower byte of Bi-directional data bus.
D7, C3, C8, C2, A7,
A2, B8, A3
DQU0−DQU7
Input/Output Data Input/Output: Upper byte of Bi-directional data bus.
F3, G3
DQSL, DQSL#
Input/Output
Lower byte data Strobe: Data Strobe output with read data, input with
write data of DQL[7:0]. Edge-aligned with read data, centered in write
data. DQSL is paired with DQSL# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
C7, B7
DQSU, DQSU#
Input/Output
Upper byte data Strobe: Data Strobe output with read data, input with
write data of DQU[7:0]. Edge-aligned with read data, centered in write
data. DQSU is paired with DQSU# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power Supply: 1.5V ± 0.075V.
A9, B3, E1, G8, J2,
J8, M1, M9, P1, P9,
VSS
T1, T9
Supply
Ground.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
VDDQ
Supply
DQ Power Supply: 1.5V ± 0.075V.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
Supply
DQ Ground.
H1
VREFDQ
Supply
Reference voltage for DQ.
M8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
External reference ball for output drive and On-Die Termination
L8
ZQ
Supply
Impedance calibration: This ball needs an external 240 Ω ± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
J1, J9, L1, L9, M7,
T3, T7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A12, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.
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Publication Release Date: Feb. 27, 2013
Revision A04