W631GG6KB-15 Datasheet, PDF (36/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
 Read:
A[1:0] = ‗00‘b (Data burst order is fixed starting at nibble, always 00b here)
A[2] = ‗0‘b (For BL=8, burst order is fixed as 0,1,2,3,4,5,6,7)
A12/BC# = 1 (use regular burst length of 8)
All other address pins (including BA[2:0] and A10/AP): don't care
 After RL = AL + CL, DRAM bursts out the pre-defined Read Calibration Pattern.
 Memory controller repeats these calibration reads until read data capture at memory controller is
optimized.
 After end of last MPR read burst, wait until tMPRR is satisfied.
 Set MRS, ―MR3 A[2] = 0b‖ and ―MR3 A[1:0] = don't care‖ to the normal DRAM state.
All subsequent read and write accesses will be regular reads and writes from/to the DRAM array.
 Wait until tMRD and tMOD are satisfied.
 Continue with ―regular‖ DRAM commands, like activate a memory bank for regular read or write
access,...
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Publication Release Date: Feb. 27, 2013
Revision A04