W631GG6KB-15 Datasheet, PDF (18/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.3.1.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values
shown in Figure 5. Programming bit A7 to a ‗1‘ places the DDR3 SDRAM into a test mode that is only
used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified
if A7 = 1.
7.3.1.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‗0‘ after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL
can be used (i.e., Read commands or ODT synchronous operations).
7.3.1.5 Write Recovery
The programmed WR value MR0 (bits A9, A10 and A11) is used for the auto precharge feature along
with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by
dividing tWR (in nS) by tCK(avg) (in nS) and rounding up to the next integer: WRmin[cycles] =
Roundup(tWR[nS]/tCK(avg)[nS]). The WR must be programmed to be equal to or larger than tWR(min).
7.3.1.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power down mode. When MR0 (A12
= 0), or ‗slow-exit‘, the DLL is frozen after entering precharge power down (for potential power savings)
and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or
‗fast-exit‘, the DLL is maintained after entering precharge power down and upon exiting power down
requires tXP to be met prior to the next valid command.
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Publication Release Date: Feb. 27, 2013
Revision A04