W631GG6KB-15 Datasheet, PDF (153/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
CK
tIS
tIH
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min _{VREF to AC}
region
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
nominal
line
VSS
ΔTF
nominal
line
tVAC
tangent
line
tangent
line
VREF to AC
region
tVAC
ΔTR
tangent line [VIH(AC)min - VREF(DC)]
Setup Slew Rate
Rising Signal
=
ΔTR
Setup Slew Rate ^{tangent line [VREF(DC) - VIL(AC)max]}
Falling Signal ⁼
ΔTF
Figure 109 – Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
- 153 -
Publication Release Date: Feb. 27, 2013
Revision A04