W631GG6KB-15 Datasheet, PDF (38/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
T0
CK#
CK
Ta
Tb0
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
T10
Td
Command
PREA
MRS
READ^*1
READ^*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
VALID
tRP
tMOD
tCCD
tMPRR
tMOD
BA
3
VALID
VALID
3
A[1:0]
0
0^*2
0^*2
VALID
A[2]
1
0^*2
0^*2
0
A[9:3]
00
VALID
VALID
00
A10/AP
1
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID^*1
VALID^*1
0
DQS, DQS#
DQ
RL
RL
NOTES: 1. RD with BL8 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[2:0].
TIME BREAK
Figure 18 – MPR Readout of pre-defined pattern, BL8 fixed burst order, back-to-back readout
DON'T CARE
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Publication Release Date: Feb. 27, 2013
Revision A04