W631GG6KB-15 Datasheet, PDF (29/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.9 Write Leveling
For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‗write leveling‘ feature to allow the controller to compensate
for skew.
The memory controller can use the ‗write leveling‘ feature and feedback from the DDR3 SDRAM to
adjust the DQS - DQS# to CK - CK# relationship. The memory controller involved in the leveling must
have adjustable delay setting on DQS - DQS# to align the rising edge of DQS - DQS# with that of the
clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK#, sampled with the rising
edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays DQS - DQS# until a
transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would
ensure tDQSS specification.
Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to
combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS -
DQS# signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH
may have to be better than the absolute limits provided in section 9.16 “AC Characteristics” in order
to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is shown in Figure 13.
T0
T1
T2
T3
T4
T5
T6
T7
Source
CK#
CK
Diff_DQS
Tn
T0
Destination
CK#
CK
T1
T2
T3
T4
T5
T6
Diff_DQS
DQ
0 or 1
0
0
0
Diff_DQS
Push DQS to capture 0-1
transition
DQ
0 or 1
1
1
1
Figure 13 – Write Leveling Concept
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on
ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM
configurations x4, x8 and x16. On a x16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The upper data
bits should provide the feedback of the upper Diff_DQS(Diff_UDQS) to clock relationship whereas the
lower data bits would indicate the lower Diff_DQS(Diff_LDQS) to clock relationship.
- 29 -
Publication Release Date: Feb. 27, 2013
Revision A04