W631GG6KB-15 Datasheet, PDF (86/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
CK#
CK
Command
Address
ODT
RTT
DQS, DQS#
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
WRS4
VALID
ODTLcnw
NOP
NOP
NOP
ODTH4
NOP
NOP
NOP
NOP
NOP
ODTLoff
NOP
NOP
ODTLon
tAONmin
ODTLcwn4
tADCmax
Rtt_WR
tADCmin
tADCmax
tAOFmin
Rtt_Nom
tAOFmax
WL
Din Din Din Din
b
b+1 b+2 b+3
TRANSITIONING
DON'T CARE
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 80 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
CK#
CK
Command
Address
ODT
RTT
DQS, DQS#
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
WRS4
VALID
ODTLcnw
NOP
NOP
NOP
ODTH4
NOP
NOP
NOP
ODTLoff
NOP
NOP
NOP
NOP
ODTLon
tAONmin
ODTLcwn4
tADCmax
Rtt_WR
tAOFmin
tAOFmax
WL
Din Din Din Din
b
b+1 b+2 b+3
TRANSITIONING
DON'T CARE
Note:
1. Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
Figure 81 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 4 clock cycles
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Publication Release Date: Feb. 27, 2013
Revision A04