W631GG6KB-15 Datasheet, PDF (106/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
9.7 DC and AC Output Measurement Levels
Table 24 – Single-ended DC and AC Output Levels
PARAMETER
SYMBOL
VALUE
UNIT NOTES
DC output high measurement level (for IV curve linearity)
VOH(DC)
0.8 x VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.5 x VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.2 x VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
VTT + 0.1 x VDDQ
V
1
AC output low measurement level (for output slew rate)
VOL(AC)
VTT - 0.1 x VDDQ
V
1
Note:
1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 25 – Differential DC and AC Output Levels
PARAMETER
SYMBOL
VALUE
MIN. MAX.
UNIT NOTES
AC differential output high measurement level (for output
slew rate)
VOH.DIFF(AC)
+0.2 x VDDQ
V
1
AC differential output low measurement level (for output
slew rate)
VOL.DIFF(AC)
-0.2 x VDDQ
V
1
Note:
1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
9.7.1 Output Slew Rate Definition and Requirements
The slew rate definition depends if the signal is single-ended or differential. For the relevant AC output
reference levels see above Table 24 and Table 25.
Table 26 – Output Slew Rate
PARAMETER
SYMBOL
Single-ended Output Slew Rate SRQse
Differential Output Slew Rate SRQdiff
DDR3-1333,
DDR3-1600
MIN.
MAX.
2.5
5
5
10
DDR3-1866
MIN.
2.5
5
MAX.
5*¹
12
UNIT
V/nS
V/nS
NOTES
1, 2, 3
2, 3
Notes:
1. In two cases, a maximum slew rate of 6 V/nS applies for a single DQ signal within a byte lane.
- Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 5 V/nS applies.
2. Background for Symbol Nomenclature: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-
Output); se: Single-ended Signals; diff: Differential Signals.
3. For RON = RZQ/7 settings only.
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Publication Release Date: Feb. 27, 2013
Revision A04