W631GG6KB-15 Datasheet, PDF (152/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
CK
CK#
DQS#
DQS
tDS
tDH
VDDQ
tIS
tIH
tDS
tDH
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
DC to VREF
region
nominal
slew rate
VIL(AC)max
nominal
slew rate
DC to VREF
region
VSS
Hold Slew Rate VREF(DC) – VIL(DC)max
Rising Signal ⁼
ΔTR
ΔTR
ΔTF
Hold Slew Rate
Falling Signal
=
VIH(DC)min - VREF(DC)
ΔTF
Figure 108 – Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe)
and tIH (for ADD/CMD with respect to clock)
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Publication Release Date: Feb. 27, 2013
Revision A04