W631GG6KB-15 Datasheet, PDF (30/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.9.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ‗High‘ and after finishing leveling, DRAM exits
from write leveling mode if A7 in MR1 set ‗Low‘ (Table 3). Note that in write leveling mode, only
DQS/DQS# terminations are activated and deactivated via ODT pin, unlike normal operation (Table 4).
Table 3 – MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
Table 4 – DRAM termination function in the leveling mode
ODT pin @DRAM
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
Asserted
On
Off
Note:
In Write Leveling Mode with its output buffer disabled (MR1 A[7] = 1 with MR1 A[12] = 1) all Rtt_Nom settings are allowed; in
Write Leveling Mode with its output buffer enabled (MR1 A[7] = 1 with MR1 A[12] = 0) only Rtt_Nom settings of RZQ/2, RZQ/4
and RZQ/6 are allowed.
7.9.2 Write Leveling Procedure
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When
entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode,
only NOP or DESELECT commands are allowed, as well as an MRS command to change Qoff bit
(MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling mode,
the MRS command performing the exit (MR1[A7]=0) may also change MR1 bits of A12, A9, A6-A5,
and A2-A1. Since the controller levels one rank at a time, the output of other ranks must be disabled
by setting MR1 bit A12 to 1. The Controller may assert ODT after tMOD, at which time the DRAM is
ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM
has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a
single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller.
tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ
bits asynchronously after tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling
feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure.
There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is
defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming DQ and
decides to increment or decrement DQS - DQS# delay setting and launches the next DQS/DQS#
pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the
controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 14
describes the timing diagram and parameters for the overall Write Leveling procedure.
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Publication Release Date: Feb. 27, 2013
Revision A04