W631GG6KB-15 Datasheet, PDF (105/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
Note:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with a
single-ended swing VSEL/VSEH of at least VDD/2 ± 250 mV, and when the differential slew rate of CK - CK# is larger
than 3 V/nS. Refer to Table 21 for VSEL and VSEH standard values.
2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX (Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX (Max)) ≥ 25mV
9.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 9.16.4 “Address / Command Setup, Hold and Derating” on page 148 for single-ended
slew rate definitions for address and command signals.
See section 9.16.5 “Data Setup, Hold and Slew Rate Derating” on page 155 for single-ended slew
rate definitions for data signals.
9.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 23 and Figure 93.
Table 23 – Differential Input Slew Rate Definition
Description
Measured
from
to
Defined by
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
VIL.DIFFmax VIH.DIFFmin
[VIH.DIFFmin - VIL.DIFFmax] / ΔTR.DIFF
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
VIH.DIFFmin VIL.DIFFmax
[VIH.DIFFmin - VIL.DIFFmax] / ΔTF.DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
ΔTR.DIFF
VIH.DIFFmin
0
VIL.DIFFmax
ΔTF.DIFF
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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Publication Release Date: Feb. 27, 2013
Revision A04