W631GG6KB-15 Datasheet, PDF (104/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
VSELmax
CK or DQS
VSS or VSSQ
VSEL
time
Figure 91 – Single-ended requirement for differential signals
Note that, while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the
same. The transition of single-ended signals through the AC-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
9.6.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the
requirements in Table 22. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS.
VDD
CK#, DQS#
VIX
VIX
VDD/2
VIX
VSEH
CK, DQS
VSEL
VSS
Figure 92 – VIX Definition
Table 22 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
DDR3-1333, DDR3-1600 & DDR3-1866
SYMBOL
UNIT
MIN.
MAX.
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK#
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS#
VIX(CK)
VIX(DQS)
- 150
- 175
-150
150
mV
175
mV
150
mV
NOTES
2
1
2
- 104 -
Publication Release Date: Feb. 27, 2013
Revision A04