W631GG6KB-15 Datasheet, PDF (156/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
DQ
Slew
rate
(V/nS)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/nS
ΔtDS ΔtDH
75
50
50
34
0
0
-
-
-
-
-
-
-
-
-
-
-
-
Table 55 – Derating values for DDR3-1333/1600 tDS/tDH - (AC150)
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
DQS, DQS# Differential Slew Rate
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
75
50
75
50
-
-
-
-
-
-
-
-
50
34
50
34
58
42
-
-
-
-
-
-
0
0
0
0
8
8
16
16
-
-
-
-
0
-4
0
-4
8
4
16
12
24
20
-
-
-
-
0
-10
8
-2
16
6
24
14
32
24
-
-
-
-
8
-8
16
0
24
8
32
18
-
-
-
-
-
-
15 -10 23
-2
31
8
-
-
-
-
-
-
-
-
14 -16 22
-6
-
-
-
-
-
-
-
-
-
-
7
-26
1.0 V/nS
ΔtDS ΔtDH
-
-
-
-
-
-
-
-
-
-
40
34
39
24
30
10
15 -10
Note: Cell contents ‗-‘ are defined as not supported.
Table 56 – Derating values for DDR3-1866 tDS/tDH - (AC135)
DQ
Slew
rate
(V/nS)
8.0 V/nS
7.0 V/nS
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
Alternate DC100 Threshold -> VIH(DC)=VREF(DC)+100mV, VIL(DC)=VREF(DC)-100mV
DQS, DQS# Differential Slew Rate
6.0 V/nS 5.0 V/nS 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
4.0 34 25 34 25 34 25 - - - - - - - - - - - - - - - - - -
3.5 29 21 29 21 29 21 29 21 - - - - - - - - - - - - - - - -
3.0 23 17 23 17 23 17 23 17 23 17 - - - - - - - - - - - - - -
2.5 - - 14 10 14 10 14 10 14 10 14 10 - - - - - - - - - - - -
2.0 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - -
1.5 - - - - - - -23 -17 -23 -17 -23 -17 -23 -17 -15 -9 - - - - - - - -
1.0 - - - - - - - - -68 -50 -68 -50 -68 -50 -60 -42 -52 -34 - - - - - -
0.9 - - - - - - - - - - -66 -54 -66 -54 -58 -46 -50 -38 -42 -30 - - - -
0.8 - - - - - - - - - - - - -64 -60 -56 -52 -48 -44 -40 -36 -32 -26 - -
0.7 - - - - - - - - - - - - - - -53 -59 -45 -51 -37 -43 -29 -33 -21 -17
0.6 - - - - - - - - - - - - - - - - -43 -61 -35 -53 -27 -43 -19 -27
0.5 - - - - - - - - - - - - - - - - - - -39 -66 -31 -56 -23 -40
0.4 - - - - - - - - - - - - - - - - - - - - -38 -76 -30 -60
Note: Cell contents ‗-‘ are defined as not supported.
Table 57 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid DQ transition
DDR3-1333/1600
DDR3-1866
Slew Rate [V/nS]
tVAC @ 150mV [pS]
tVAC @ 135mV [pS]
tVAC @ 135mV [pS]
Min.
Max.
Min.
Max.
Min.
Max.
> 2.0
105
-
113
-
93
-
2.0
105
-
113
-
93
-
1.5
80
-
90
-
70
-
1.0
30
-
45
-
25
-
0.9
13
-
30
-
Note
-
0.8
Note
-
11
-
Note
-
0.7
Note
-
Note
-
Note
-
0.6
Note
-
Note
-
Note
-
0.5
Note
-
Note
-
Note
-
< 0.5
Note
-
Note
Note
-
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than
VIL(AC) level.
- 156 -
Publication Release Date: Feb. 27, 2013
Revision A04