W631GG6KB-15 Datasheet, PDF (13/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be
undefined). RESET needs to be maintained for minimum 100 nS. CKE is pulled ―LOW‖ before
RESET being de-asserted (min. time 10 nS).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, CK#
tCKSRX
VDD, VDDQ
T = 100 ns
T = 500 µs
RESET#
CKE
Command
tIS
Tmin = 10 ns
tDLLK
tXPR
tIS
tMRD
tMRD
tMRD
tMOD
*1
MRS
MRS
MRS
MRS
ZQCL
tZQinit
*1
VALID
VALID
BA
ODT
MR2
MR3
MR1
MR0
tIS
Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
VALID
tIS
VALID
RTT
TIME BREAK
DON'T CARE
Note:
1. From time point ―Td‖ until ―Tk‖ NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 2 – Reset Procedure at Power Stable Condition
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Publication Release Date: Feb. 27, 2013
Revision A04