W631GG6KB-15 Datasheet, PDF (101/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA and VREFDQ are
illustrated in Figure 89. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands
for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g., 1 sec). This average
has to meet the min/max requirements in Table 17. Furthermore VREF(t) may temporarily deviate from
VREF(DC) by no more than ± 1% VDD.
voltage
VREF(DC)
VREF AC-noise
VREF(t)
VDD
VREF(DC)max
VDD/2
VREF(DC)min
VSS
time
Figure 89 – Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are
dependent on VREF.
―VREF‖ shall be understood as VREF(DC), as defined in Figure 89.
This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a
valid high or low level and therefore the time to which setup and hold is measured. System timing and
voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-
eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time
and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up
to the specified limit (± 1% of VDD) are included in DRAM timings and their associated deratings.
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Publication Release Date: Feb. 27, 2013
Revision A04