W631GG6KB-15 Datasheet, PDF (2/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.7.2
DLL ―off‖ to DLL ―on‖ Procedure.......................................................................................26
7.8 Input clock frequency change..............................................................................................................27
7.8.1
Frequency change during Self-Refresh............................................................................27
7.8.2
Frequency change during Precharge Power-down ..........................................................27
7.9 Write Leveling .....................................................................................................................................29
7.9.1
DRAM setting for write leveling & DRAM termination function in that mode ....................30
7.9.2
Write Leveling Procedure.................................................................................................30
7.9.3
Write Leveling Mode Exit .................................................................................................32
7.10 Multi Purpose Register ........................................................................................................................33
7.10.1
MPR Functional Description.............................................................................................34
7.10.2
MPR Register Address Definition.....................................................................................35
7.10.3
Relevant Timing Parameters............................................................................................35
7.10.4
Protocol Example .............................................................................................................35
7.11 ACTIVE Command..............................................................................................................................41
7.12 PRECHARGE Command ....................................................................................................................41
7.13 READ Operation .................................................................................................................................42
7.13.1
READ Burst Operation .....................................................................................................42
7.13.2
READ Timing Definitions..................................................................................................43
7.13.2.1
READ Timing; Clock to Data Strobe relationship....................................................44
7.13.2.2
READ Timing; Data Strobe to Data relationship .....................................................45
7.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .............................................46
7.13.2.4
tRPRE Calculation..................................................................................................47
7.13.2.5
tRPST Calculation ..................................................................................................47
7.13.2.6
Burst Read Operation followed by a Precharge......................................................53
7.14 WRITE Operation................................................................................................................................55
7.14.1
DDR3 Burst Operation .....................................................................................................55
7.14.2
WRITE Timing Violations .................................................................................................55
7.14.2.1
Motivation ...............................................................................................................55
7.14.2.2
Data Setup and Hold Violations..............................................................................55
7.14.2.3
Strobe to Strobe and Strobe to Clock Violations.....................................................55
7.14.2.4
Write Timing Parameters ........................................................................................55
7.14.3
Write Data Mask...............................................................................................................56
7.14.4
tWPRE Calculation...........................................................................................................57
7.14.5
tWPST Calculation ...........................................................................................................57
7.15 Refresh Command ..............................................................................................................................64
7.16 Self-Refresh Operation .......................................................................................................................66
7.17 Power-Down Modes............................................................................................................................68
7.17.1
Power-Down Entry and Exit .............................................................................................68
7.17.2
Power-Down clarifications - Case 1 .................................................................................74
7.17.3
Power-Down clarifications - Case 2 .................................................................................74
7.17.4
Power-Down clarifications - Case 3 .................................................................................75
7.18 ZQ Calibration Commands..................................................................................................................76
Publication Release Date: Feb. 27, 2013
Revision A04
-2-