W631GG6KB-15 Datasheet, PDF (31/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
CK#^*5
CK
Command
MRS^*2
ODT
Diff_DQS^*4
One Prime DQ:
Prime DQ^*1
Late Remaining DQs
NOP^*3
tMOD
NOP
NOP
tWLDQSEN
tWLMRD
T1
tWLH
tWLS
NOP
NOP
NOP
tDQSL^*6
tDQSH^*6
tWLO
tWLO
Early Remaining DQs
tWLO
All DQs are Prime:
tWLMRD
tWLO
Late Prime DQs^*1
Early Prime DQs^*1
tWLO
T2
tWLS
tWLH
NOP
NOP
NOP
NOP
NOP
tDQSL^*6
tDQSH^*6
tWLO
tWLOE
tWLOE
tWLO
tWLO
tWLOE
UNDEFINED DRIVING MODE
TIME BREAK
DON'T CARE
Notes:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the
remaining DQs must be driven low, as shown in above Figure, and maintained at this state through out the leveling
procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. Diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with
solid line, DQS# is shown with dotted line.
5. CK, CK#: CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the
max pulse width is system dependent.
Figure 14 – Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low at
T1 and CK - CK# high at T2]
- 31 -
Publication Release Date: Feb. 27, 2013
Revision A04