W631GG6KB-15 Datasheet, PDF (80/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
CK#
CK
CKE
ODT
DRAM_RTT
CK#
CK
CKE
Command
ODT
DRAM_RTT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
AL = 3
AL = 3
CWL - 2
ODTH4min
ODTLon = CWL + AL - 2
tAONmin
tAONmax
ODTLoff = CWL + AL - 2
Rtt_Nom
tAOFmin
tAOFmax
TRANSITIONING
DON'T CARE
Figure 74 – Synchronous ODT Timing (AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
ODTH4
NOP
NOP
NOP
WRS4
NOP
NOP
ODTH4min
ODTH4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLon = WL - 2
tAONmin
ODTLoff = WL - 2
ODTLon = WL - 2
tAONmax
Rtt_Nom
tAOFmin
tAOFmax
tAONmax
tAONmin
Figure 75 – Synchronous ODT (BL = 4, WL = 7)
ODTLoff = WL - 2
tAOFmin
tAOFmax
TRANSITIONING
DON'T CARE
- 80 -
Publication Release Date: Feb. 27, 2013
Revision A04