W631GG6KB-15 Datasheet, PDF (33/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.10 Multi Purpose Register
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration
bit sequence. The basic concept of the MPR is shown in Figure 16.
Memory Core
(all banks precharged)
MR3 [A2]
Multipurpose register
Pre-defined data for Reads
DQ, DM, DQS, DQS#
Figure 16 – MPR Block Diagram
To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 Register with bit
A2 = 1, as shown in Table 5. Prior to issuing the MRS command, all banks must be in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command
is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown in Table 6. When the
MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued
with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a
READ command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-
Refresh, and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET
function is supported during MPR enable mode.
MR3 A[2]
MPR
0b
1b
Table 5 – MPR Functional Description of MR3 Bits
MR3 A[1:0]
Function
MPR-Loc
don't care
(0b or 1b)
See Table 6
Normal operation, no MPR transaction
All subsequent Reads will come from DRAM array
All subsequent Write will go to DRAM array
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]
- 33 -
Publication Release Date: Feb. 27, 2013
Revision A04