W631GG6KB-15 Datasheet, PDF (32/158 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB
7.9.3 Write Leveling Mode Exit
The following sequence describes how the Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From
now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the
respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and continue registering low. (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be
issued after tMRD (Td1).
CK#
CK
Command
Address
ODT
RTT_DQS_DQS#
DQS_DQS#
RTT_DQ
DQ^*1
T0
NOP
T1
T2
NOP
NOP
Rtt_Nom
tWLO + tWLOE
Ta0
Tb0
Tc0
Tc1
NOP
NOP
NOP
NOP
tIS
tAOFmin
ODTLoff
tAOFmax
result = 1
Tc2
MRS
MR1
Td0
Td1
Te0
Te1
NOP
tMRD
VALID
VALID
tMOD
NOP
VALID
VALID
UNDEFINED DRIVING MODE
TRANSITIONING
TIME BREAK
DON'T CARE
Note:
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
Figure 15 – Timing details of Write leveling exit
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Publication Release Date: Feb. 27, 2013
Revision A04